1. Field of the Invention
This invention relates to the field of testing semiconductor devices for defects, and more specifically, to a method for detecting defects in a semiconductor device using IDDQ testing in the presence of high background leakage current.
2. Background Information
In the manufacture of semiconductor devices it is important to have methods for testing a device, for example a transistor, and determining if it is a good device or if it contains defects before selling such a product to a customer. Some methods of testing a device for defects use a "modeling" system. In a modeling system there is at least one device which is presumably not defective. This non-defective model (model) is tested and the results are stored in a memory. Other devices which are like the model are then tested and the results of the tested devices are compared to the results of the model. If the results are the same or are within a manufacturer's tolerance levels (i.e. a manufacturer's acceptable ranges for deviation from the model) then the device is presumably a good or non-defective device and may be sold to a customer. If the results are not the same and are not within the manufacturer's tolerance levels then the device is a defective device and cannot be sold to a customer.
Another method for testing a device for defects is called IDDQ Testing. In a CMOS device when the clock is stopped, the device is said to be in a quiescent state, thus the current in the device is called drain to drain quiescent current (IDDQ). When the clock is running the device is said to be in active state, thus the current in the device is called drain to drain dynamic current (IDDD). In IDDQ testing, a device is tested by measuring the current while the device is in the quiescent state. Measuring the quiescent current allows defects such as open and short circuits to be detected. If the IDDQ is above a preset threshold, then the device is termed "defective" and is not sold to the customer.
Prior methods for IDDQ testing require a low background leakage current while in the quiescent state. In such prior methods, the background leakage current is typically in the range of a few hundred nanoamps (nA) to a few hundred microamps(.mu.A). As is illustrated in FIG. 1, a statistical sample of devices under test (DUT) is taken in order to determine a median background leakage current 110. Once a median background leakage current is established then an IDDQ pass/fail limit 120 is set. The pass/fail limit must be set such that it is greater than the median background leakage current but such that it is less than the average current caused by a device defect. Typically in prior methods the pass/fail limit is set at a current much higher than the median, usually from three (3) to six (6) standard deviations greater than the median background leakage current. For example, the pass/fail limit may be in the range of approximately 500 microamps (.mu.A) to 1.5 milliamps (mA). Any device exhibiting an IDDQ current greater than the pass/fail limit is a defective device 130 and is not sold to a customer.
One of the problems with prior art methods for IDDQ testing is that they can only detect defects where the defect causes an IDDQ current larger than the background leakage current. As device characteristics of semiconductors become smaller and more dense, the IDDQ current caused by defects becomes smaller than the background leakage current.
Because semiconductor devices are becoming smaller, so too are the dimensions of the components that make up those devices. Consequently, the channel lengths of such smaller devices also become very small or short. These shorter channel lengths lead to a substantial increase in the background leakage current. For example in submicron devices, background leakage currents in the range of approximately several tens of milliamps (mA) are likely due to the short channel lengths.
As is illustrated in FIG. 2, with smaller and more dense semiconductor devices a median background leakage current 210 which is on the order of tens of milliamps (mA) is larger than the typical pass/fail limit 220 which is on the order of several hundred microamps (.mu.A). Thus a defect higher than the pass/fail limit 220 but smaller than the background leakage current 210 would go undetected. If the pass/fail limit was set three (3) to six (6) times the median 210, then the pass/fail limit would be so high that virtually all defects would go undetected, making this prior technique impractical. The defective devices in essence will not have a defect current large enough to distinguish itself from the median background leakage current 210 of the device.
Thus, what is needed is a method for detecting defects in a semiconductor device in the presence of a high background leakage current.